Algorithms/Software Analysis

As we have observed from several research outcomes, with the deep convergence of AI and HPC, computational performance is no longer determined by isolated algorithms or hardware components, but by the coordinated optimization of the entire Algorithm–Compiler–Hardware stack. However, existing benchmarks typically focus on individual operators or single metrics, making them inadequate for capturing the true performance and energy-efficiency characteristics arising from cross-layer interactions. To address this limitation, we will be using systematic, multi-level evaluation framework spanning four tiers—Basic-operations (ε), MICRO (μ), MACRO (M), and Simulations (S)—where higher-level workloads are progressively composed of lower-level building blocks in terms of complexity. This framework aims to break the traditional software–hardware “black box” and establish a unified and comparable performance standard across heterogeneous architectures (CPU, GPU, NPU, etc) and programming languages, thereby redefining how computational efficiency is understood and evaluated.

Methodologically, we have developed combined approach of bottom-up performance diagnosis to complement top-down system-level evaluation. We have constructed a curated suite of representative workloads covering 30 application domains, including scientific computing, graph algorithms, compiler optimizations, cryptography, deep learning, and many others. Each workload is accompanied by standardized pseudocode and reference implementations to ensure reproducibility and cross-platform consistency. Within the AI domain, we decouple the model training pipeline into operator-level micro-benchmarks, optimizer overheads, and end-to-end workflows, enabling “pixel-level” localization of performance bottlenecks. This framework is expected to deliver value to both academia and industry as it will provide researchers with a reproducible methodology for quantitatively assessing the marginal benefits of new algorithms or compilation techniques, while offering hardware designers and system engineers a practical tool to identify performance and energy inefficiencies, thereby guiding the co-design and optimization of next-generation high-efficiency computing systems.